1. Field of the Invention
The present invention generally relates to Hardware Description Language (HDL) processing methods and computer-readable storage media, and more particularly to a HDL processing method for processing the HDL in Computer Aided Design (CAD) which supports design of hardware, and to a computer-readable storage medium which stores a program for causing a computer to process the HDL.
2. Description of the Related Art
Conventionally, when processing the HDL, the processing, such as logic synthesis of the HDL and compiling of the logic simulation, is carried out in a single path and not in divisions, as proposed in Japanese Laid-Open Patent Applications No. 7-334548 and No. 9-251480, for example. The logic synthesis of the HDL includes inputting a description of the Resistor Transfer Level (RTL) in a high-level programming language such as the HDL, and processing the description into a description of the Net List in a programming language lower in level compared to the high-level programming language such as the HDL. The processing of the HDL in divisions, in units of blocks, is proposed in Japanese Laid-Open Patent Applications No. 9-330339 and No. 7-78189, for example. In addition, a method of successively processing the HDL for each hierarchical level (or hierarchical layer) from the low hierarchical level is proposed in a Japanese Laid-Open Patent Application No. 2000-148805, for example. Moreover, a method of processing the HDL in parallel for each hierarchical level is proposed in a Japanese Laid-Open Patent Application No. 1-304541, for example.
Recently, the logic scale of Large Scale Integrated circuits (LSIs) has increased considerably, and there are demands to develop the LSI in a short period of time. For this reason, there is a need to reduce the time required for the logic design stage of the LSI development. However, in the conventional logic design stage, the time required to execute the CAD tool for the logic synthesis of the HDL or the logic simulation is not short.
According to the conventional method which does not carry out the processing of the HDL in divisions, the process cannot be executed in parallel in a distributed manner by a plurality of Central Processing Units (CPUs) and a long execution time is required, because the processing, such as the logic synthesis of the HDL and the compiling of the logic simulation, is carried out in a single path. In addition, since the processing is carried out in the single path, a large amount of computer resources such as memories is temporarily used.
On the other hand, the conventional method which carries out the processing of the HDL in divisions does not take into consideration the hierarchical design written in HDL or the parallel execution of the process in the distributed manner.
According to the method of successively processing the HDL for each hierarchical level from the low hierarchical level as proposed in the Japanese Laid-Open Patent Application No. 2000-148805, the parallel execution of the process is impossible. Furthermore, because it is a precondition in the Japanese Laid-Open Patent Application No. 2000-148805 that the configuration statement is written in the Very High-Speed IC (VHSIC) HDL (or simply VHDL), the process cannot be carried out in a language, such as the HDL, which is other than the VHDL, since the grammar corresponding to the configuration statement does not exist in the HDL or the like.
The method of processing the HDL in parallel for each hierarchical level as proposed in the Japanese Laid-Open Patent Application No. 1-304541 can only treat two hierarchical levels, namely, the parent and the child levels. In addition, the processing of the general HDL is impossible because this proposed method cannot cope with a situation where a plurality of instances exist in a certain hierarchical level.